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This publication is protected by law and its content is only available in certain networks in Silesian University of Technology. Employees and Students of the Silesian University of Technology can gain access through the HAN authentication system
This publication is protected by law and its content is only available in certain networks in Silesian University of Technology. Employees and Students of the Silesian University of Technology can gain access through the HAN authentication system

Title: Energooszczędny dekoder kodów LDPC implementowany w układzie FPGA ; Low power LDPC code decoder implemented in FPGA structure

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Last modified:

Jan 7, 2022

In our library since:

Nov 3, 2021

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2

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https://repolis.bg.polsl.pl/publication/81429

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Rozprawa doktorska Jan 7, 2022

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